From 7a433404c5d84bfdda06c37ac7a7a1562f0ebd56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=91=89=E7=9C=9F?= Date: Sat, 20 Nov 2021 10:32:48 +0800 Subject: [PATCH 1/3] rk628: rgb2lvds display clock abnormally Change-Id: Idc1e26416cdb7eb5111f09264cb4aab63adcefa7 --- drivers/gpu/drm/rockchip/rk628/rk628_lvds.c | 5 ++--- drivers/gpu/drm/rockchip/rk628/rk628_post_process.c | 2 ++ 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_lvds.c b/drivers/gpu/drm/rockchip/rk628/rk628_lvds.c index b0b6dcedd00b..92efed041cf0 100644 --- a/drivers/gpu/drm/rockchip/rk628/rk628_lvds.c +++ b/drivers/gpu/drm/rockchip/rk628/rk628_lvds.c @@ -192,7 +191,7 @@ static void rk628_lvds_bridge_enable(struct drm_bridge *bridge) SW_LVDS_CON_CLKINV(0); regmap_write(lvds->grf, GRF_LVDS_TX_CON, val); - bus_width |= (mode->clock / 1000) << 8; + bus_width |= (mode->crtc_clock / 1000) << 8; phy_set_bus_width(lvds->phy, bus_width); ret = phy_set_mode(lvds->phy, PHY_MODE_VIDEO_LVDS); @@ -247,7 +246,7 @@ static void rk628_lvds_bridge_mode_set(struct drm_bridge *bridge, struct drm_display_mode *adj) { struct rk628_lvds *lvds = bridge_to_lvds(bridge); - + printk("lvds mode clock - %d,crtc_clock -%d\n",adj->clock,adj->crtc_clock); drm_mode_copy(&lvds->mode, mode); } diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_post_process.c b/drivers/gpu/drm/rockchip/rk628/rk628_post_process.c index fc4ea7408ec5..39582cf9ac5f 100644 --- a/drivers/gpu/drm/rockchip/rk628/rk628_post_process.c +++ b/drivers/gpu/drm/rockchip/rk628/rk628_post_process.c @@ -283,6 +283,8 @@ static void rk628_post_process_bridge_mode_set(struct drm_bridge *bridge, else drm_mode_copy(&pp->dst_mode, &pp->src_mode); + pp->src_mode.clock = pp->src_mode.crtc_clock; + pp->dst_mode.clock = pp->dst_mode.crtc_clock; /* hdmirx 4k-60Hz mode only support yuv420 */ if (pp->src_mode.clock == 594000) regmap_write(pp->grf, GRF_CSC_CTRL_CON, SW_Y2R_EN(1)); -- 2.25.1